1. Field of the Invention
The present invention relates to a digital computation integrated circuit and, more particularly, to a digital computation integrated circuit including a circuit preferably applicable to developing an instruction program.
2. Description of the Prior Art
A known conventional digital computation integrated circuit outputs a control signal in accordance with the instruction program stored in an instruction memory.
Such a conventional digital computation integrated circuit is constructed to sequentially execute instruction data stored in an instruction memory in the order of addresses. Furthermore, this digital computation integrated circuit is so constructed as to allow an instruction (hereinafter called a [branch instruction]) to designate an address of instruction data to be executed next and an instruction (hereinafter referred to as a [repetitive instruction]) to repeatedly execute the same instruction for a predetermined number of times.
A description of such a digital computation integrated circuit will hereafter be given by exemplifying a digital computation integrated circuit that allows the branch instruction.
Referring to FIG. 6, when switching ON a power supply, a control signal 110 is set at a low level. Consequently, a program address selector 103 directly outputs a value inputted from an adder 102. Further, an output value from this program address selector 103 is inputted directly to an address counter register 104. The value inputted thereto is outputted to an instruction memory 105 in synchronization with a next system clock o.
An instruction program is stored in the instruction memory 105. Outputted is instruction data stored in the same address as the value inputted from the address counter register 104. For instance, if the input value from the address counter register 104 is [001], the instruction memory 105 outputs the instruction data stored in an address [001].
The instruction data outputted from the instruction memory 105 is temporarily stored in an instruction register 106. The instruction data is then inputted to an instruction decoder 107 in synchronization with the next system clock o.
This instruction decoder 107 decodes the instruction data inputted. If the instruction data does not represent a branch instruction, this instruction data is converted into a control signal and outputted. At this moment, the instruction decoder 107 holds the selection signal 110 as it remains at the low level. Hence, the program address selector 103 directly outputs the input value from the adder 102, consecutively. Hereupon, the adder 102 adds [1] to the value inputted from the address counter register 104 and then outputs the added value. The address of the instruction data outputted from the instruction memory 105 therefore turns out a next address of the instruction data outputted last time. For example, if the address of the instruction data outputted last time is an address [001], instruction data in an address [002] is to be outputted this time.
On the other hand, when the decoded instruction data represents a branch instruction, the instruction decoder 107 alters the selection signal 110 to a high level. Simultaneously, this instruction data is transferred as a branch instruction signal 111 to a branch address generating circuit 101. The branch address generating circuit 101 generates an address signal indicating a branching address from this branch instruction signal 111 and outputs it to the program address selector 103. At this moment, the program address selector 103, because of the selection signal 110 assuming the high level, outputs the address inputted from this branch address generating circuit to the address counter register 104. The instruction data stored in the branching address is thereby outputted from the instruction memory 105.
Control by a control unit (not shown) can be conducted in accordance with the instruction program stored in this instruction memory 105.
The address of each instruction data executed in this manner is stored as a piece of data in an address memory 108.
Connected to this address memory 108 is an address generator 109 for sequentially generating addresses starting from a predetermined address (e.g., an address [000]). The address generator 109 is constructed of: a latch 109a for sequentially outputting an address signal for designating a memory address of the address memory 108 in accordance with the system clock o; and an adder 109b for adding [1] to an output of this latch 109a after fetching this output and transmitting the added value back to the latch 109a.
The address memory 108 sequentially stores the output values of the address counter register 104 in the addresses designated by this address generator 109. For instance, if the addresses outputted from the address counter register 104 are [000], [001] and [005] (i.e., [001] is the branch instruction), the address data [000] is stored in the address [000] of the address memory 108. The address data [001] is stored in the address 001, and [005] is stored in the address [002], respectively.
Users can confirm whether or not the instruction program stored in the instruction memory 105 is executed according to a user's intentions on the basis of stored contents of this address memory 108. Namely, the instruction program can be thereby easily debugged.
A processing speed of the digital computation integrated circuit is enhanced with an increasingly sophisticated technology of the integrated circuit in recent years. With this enhancement, the instruction program becomes more and more complex.
Under such circumstances, the above-mentioned conventional digital computation integrated circuit requires the address memory 105 having a remarkably large storage capacity. This results in an increase in costs.
Exemplifying a digital computation integrated circuit for executing the instruction program consisting of a series of instruction data repeatedly at 8 kHz, each execution time is 125 .mu.sec. Hence, the time needed for executing 1-step instruction data is 100 nsec. On this assumption, it is possible to execute the instruction program up to 1250 steps each time. Therefore, the address memory 105 may have a capacity enough to store 1250 pieces of address data.
In contrast, when the processing speed is enhanced, the time required for executing the 1-step instruction data is 50 nsec. In this case, it is feasible to execute the instruction program up to 2500 steps each time. The address memory 105 capable of storing 2500 pieces of address data is therefore required.
Moreover, a further amount of memory capacity is required when a processing is executed by a collective unit as performed in frame processing. For example, if there are 160 sampling data at 8 kHz, the total number of sampling data to be prosecuted within 125 .mu.sec is 2500.times.160, so that considerable memory capacity will be necessary.
As described above, the conventional digital computation integrated circuit needs the address memory 105 having a capacity capable of storing at least the same number of address data as the number of steps of the instruction data to be processed. For this reason, there exists a necessity for increasing the storage capacity of the address memory 105 with a greater number of steps that can be processed in one execution.